Conventional lead borate solder glasses have been extremely successful in the production of hermetic seals in semiconductor ceramic packaging. These sealing glasses are particularly useful in package geometries where two ceramic slabs sandwich a metal lead frame imbedded in glass. This design is embodied in ceramic dual in-line packages (CerDips), ceramic quad in-line packages (CerQuads) and their variations. These conventional solder glasses, however, require a sealing cycle above 400.degree. C., typically 430.degree. C. or higher. These temperatures are now considered on the high side for the more recent very large-scale integrated (VLSI) silicon devices.
This invention addresses the problem of sealing semiconductor devices in hermetic ceramic packages with a low temperature sealing glass. Since the onset of integrated circuits fabricated on silicon single crystal wafers around 1964, very fast semiconductor devices have been designed by a process known as bipolar technology which relies on deep diffusion silicon structures. These devices being somewhat temperature and surface insensitive were readily alloyed, die attached and hermetically sealed in alumina ceramic packages in the temperature range of 450.degree. to 500.degree. C.
A rapidly growing competing design technology based not on pn junction high current injection but on surface capacitive channel switching is referred to as Complementary Metal Silicon Oxide Semiconductor (CMOS). emos requires much less power to operate. The speed of emos designs is increasing so quickly they will soon outstrip almost all competing semiconductor technologies with a concurrent impact in portable, work station and mainframe computers. This increased operational speed in CMOS is, however, critically dependent on submicron scale masking technology, which itself is very sensitive to package sealing temperatures.
Very large scale integrated semiconductor devices (VLSI) such as large 300 to 600 mil square CMOS and BiPolar CMOS (BICMOS) silicon chips are quite sensitive to the thermal processes required during their last fabrication steps. These steps include metal contact alloying, die attach and final seal. These are presently performed in the 430.degree. C. range for several minutes.
The thermal sensitivity of CMOS semiconductor devices arises due to the presence of extremely dense, compact, ultrafine metallization lines reaching a fraction of a micron in width combined with ultrathin dielectric films reaching the 100 Angstrom thickness range. These three-dimensional surface interconnection patterns are prone to immediate or longer term failure modes such as metal diffusion, alloying and dielectric punch-through.
Industry consensus indicates that these fabrication steps should be made below 400.degree. C. and preferably close to 380.degree. C. to insure greater fabrication yields, throughput, and long term reliability.
It is an object of this invention to provide a sealing glass composition which can achieve a hermetic seal to alumina ceramics below 400.degree. C. in a short time (10 minutes), preferably in the 380.degree. C. range or lower and capable of withstanding extended thermal shocks. The glass seal satisfies the desired characteristics such as thermal stress resistance, insensitivity to plating acids, high electrical resistivity and low dielectric constant.
A prior patent, U.S. Pat. No. 4,186,023 issued to Dumesnil et al., discloses the use of both cuprous oxide and fluorine as joint additives to lead borate. The present application extends this approach by the addition of thallic oxide, cuprous oxide and fluorine as a ternary combination in a specific preferred molar ratio of about 1 Cu: 1 Tl: 1 F. This provides an unexpected and unusually large lowering in the softening point and viscosity in the resulting glass without affecting the glass stability against early recrystallization.